Course subtitle

This course is totally about VLSI design practical approach and it’s related to another thing which is basic for design VLSI.

What will students learn in this course?

The students are going to learn about physical design, the very essential process to make an integrated chip. This process of physical design consists of various steps and all of them are interrelated.

We have designed this video lecture to provide students in-depth exposure to the subject with clarity that none of the material is out of the prescribed syllabus.

Each part has consisted of the brief but necessary information with the entire requisite.

Who are the target students?

All the undergraduate, graduate, and working professionals who are in need to have a quick and appropriate knowledge platform.

They would get necessary and required information with crystal clear diagrams and graphics.

Course description

The design and optimization of integrated circuits (ICs) are essential to the

production of new semiconductor chips.

The design-cycle of VLSI-chips consists of different consecutive steps from high-

level synthesis (functional design) to production (packaging).

The physical design is the process of transforming a circuit description into the

physical layout, which describes the position of cells and routes for the

interconnections between them

The physical design produces an Integrated chip for use in application ranging from

military, consumer appliances, entertainment gadgets, mobile, and so on.

The main concern is the physical design of VLSI-chips is to find a layout with

minimal area, further the total wire length has to be minimized

Due to its complexity, the physical design is normally broken in various sub-steps:

1. First, the circuit has to be partitioned to generate some (up to 50) macrocells.

2. In the floorplanning phase, the cells have to be placed on the layout surface.

3. After placement, global routing has to be done. In this step the `loose'

routes for the interconnections between the single modules (macrocells) are

determined.

4. In the detailed routing, the exact routes for the interconnection wires in the

channels between the macrocells have to be computed.

5. The last step in the physical design is the compaction of the layout, where it

is compressed in all dimensions so that the total area is reduced.

This classical approach of the physical design is strongly serial with many

interdependencies between the sub-steps.

This course is updated every week

Thanks.

Course Curriculum

Vlsi Essential Concept Promo 00:01:00
L 17-Parasitics Extractions 00:19:00
L 16-Routing and Design Rule Check 00:20:00
L 14-Crosstalk Delta Delay Analysis 00:33:00
L 13-Glitch Examples And Factors Affecting Glitch Height 00:33:00
L 11-Crosstalk introduction 00:34:00
L 10-Static Timing Analysis With Real Clocks 00:36:00
L 09 -Clock Tree Optimization Checklist 00:19:00
31 Placement — Netlist Binding And Placement 00:12:00
L54 -CTS Power and CrossTalk Check 00:10:00
L 55 -Glitches quality Check 00:27:00
L 53-latency and power check (cts) 00:11:00
L 52-Duty Cycle and Latency Check 00:11:00
L 51 – Introduction to clock tree Synthesis 00:17:00
L83-CMOS matching switching resistance solution 00:14:00
L 8.2-H-Tree Pulse Width Check And Issues With Regular Buffers 00:13:00
L 8.1 FH tree Buffering Observation 00:10:00
L 1 – Physiacl Design Flow Overview1 00:31:00
L 2 FloorPlanning 00:27:00
L 3.2- Placement 00:11:00
L 3.3-placement optimization 2 00:08:00
L 4.1-Setup time analysis and set up of flip flop 00:10:00
L 4.2-setup time analysis with multiple clock2 00:10:00
L 4.3-Multiple Clock Timing Analysis And Introduction To Data Slew Check 00:11:00
L 4.4-timing analysis for data slew check 00:06:00
L 6-H tree 00:27:00
L 7.1-clock tree modelling 00:08:00
L 7.2-clockl building 00:16:00
L 7.3-CLOCK TREE OBSERVATION 00:12:00
L 10 -Static Timing Analysis With Real Clocks 00:35:00
L 12 -Glitch Examples And Factors Affecting Glitch Height 00:33:00
L 19-Basics of MOS transistor 00:40:00
L 20-Setup and Hold Timing analysis 00:30:00
Vlsi Essential Concept Promo 00:01:00
L 17-Parasitics Extractions 00:19:00
L 16-Routing and Design Rule Check 00:20:00
L 14-Crosstalk Delta Delay Analysis 00:33:00
L 13-Glitch Examples And Factors Affecting Glitch Height 00:33:00
L 11-Crosstalk introduction 00:34:00
L 10-Static Timing Analysis With Real Clocks 00:36:00
L 09 -Clock Tree Optimization Checklist 00:19:00
3.1 Placement — Netlist Binding And Placement FREE 00:12:00
Static Timing Analysis With Real Clocks FREE 00:35:00
Placement(Netlist Binding and Placement) (1) FREE 00:06:00
placement optimization 2 (1) FREE 00:08:00
Placement optimization 1 (1) FREE 00:11:00
L 5.1-Introduction to clock tree Synthesis (1) FREE 00:18:00
Drivers and Communications final FREE 00:20:00
CTS Power and CrossTalk Check (1) FREE 00:10:00

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